HCF4095B - STMicroelectronics

HCF4095B GATE J-K MASTER-SLAVE FLIP-FLOPS

OF B SERIES CMOS DEVICES” inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation. EY (Plastic Package) F (Ceramic Package) DESCRIPTION The HCC4095B/4096B (extended temperature range) and HCF4095B/4096B (intermediate temperature range) are monolithic .

Features

he gated J-K input control transfer of information into the master section during clocked operation. Information on the J-K PIN CONNECTIONS 4095B 4096B M1 (Micro Package) C1 (Chip Carrier) ORDER CODES : HCC40XXBF HCF40XXBM1 HCF40XXBEY HCF40XXBC1 September 1988 1/13 HCC/HCF4095B HCC/HCF4096B FUNCTIONAL DIAGRAMS LOGIC DIAGRAM TRUTH TABLES SYNCHRONOUS OPERATION (S=0 R=0) Inputs Before Positive Clock Transition J
* 0 0 1 1 K
* 0 1 0 1 Outputs After Positive Clock Transition Q No Change 0 1 Toggles 1 0 Q ASYNCHRONOUS OPERATION (J and K DON’T CARE) S 0 0 1 1 0 = VSS, 1 = VDD R 0 1 0 1 Q No .