Table Symbol SA NC R W BW0–BW3 NW0–NW1 K K C C TMS TDI TCK TDO VREF ZQ Qn Dn Doff CQ CQ VDD VDDQ VSS Note: NC = Not Connected to die or any other pin Description Synchronous Address Inputs No Connect Synchronous Read Synchronous Write Synchronous Byte Writes Nybble Write Control Pin Input Clock Input Clock Output Clock Output Clock Test Mode Select Test Dat.
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/
–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
• Pin-compatible with present 9Mb and 18Mb and future 72Mb and 144Mb de.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | GS8342D09E-300 |
GSI Technology |
36Mb SigmaQuad-II Burst | |
2 | GS8342D09E-167 |
GSI Technology |
36Mb SigmaQuad-II Burst | |
3 | GS8342D09E-200 |
GSI Technology |
36Mb SigmaQuad-II Burst | |
4 | GS8342D09E-250 |
GSI Technology |
36Mb SigmaQuad-II Burst | |
5 | GS8342D09AE |
GSI Technology |
36Mb SigmaQuad-II Burst of 4 SRAM | |
6 | GS8342D09BD |
GSI Technology |
36Mb SigmaQuad-II Burst of 4 SRAM | |
7 | GS8342D06BD |
GSI Technology |
36Mb SigmaQuad-II+ Burst of 4 SRAM | |
8 | GS8342D06BGD |
GSI Technology |
36Mb SigmaQuad-II+ Burst of 4 SRAM | |
9 | GS8342D07BD |
GSI Technology |
36Mb SigmaQuad-II+ Burst of 4 SRAM | |
10 | GS8342D07BGD |
GSI Technology |
36Mb SigmaQuad-II+ Burst of 4 SRAM | |
11 | GS8342D08AE |
GSI Technology |
36Mb SigmaQuad-II Burst of 4 SRAM | |
12 | GS8342D08BD |
GSI Technology |
36Mb SigmaQuad-II Burst of 4 SRAM |