ESD3V3U4ULC - Infineon

ESD3V3U4ULC Transient Voltage Suppressor Diodes

Pin 9 Pin 8 Pin 7 Pin 6 Pin 1 I/O Pin 2 I/O Pin 4 I/O Pin 5 I/O GND Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 3 b) Schematic diagram a) Pin configuration Figure 1 Table 1 Type ESD3V3U4ULC Pin Configuration and Schematic Diagram Ordering Information Package TSLP-9-1 Configuration 4 lines, uni-directional Marking code Z2 Final Data Sheet 4 Rev. 1.2.

Features

•
•
•
•
•
• ESD / transient protection of high speed data lines exceeding :
  – IEC61000-4-2 (ESD) : ±20 kV (air/contact)
  – IEC61000-4-4 (EFT) : 2.5 kV (5/50ns)
  – IEC61000-4-5 (Surge) : 3 A (8/20μs) Maximum working voltage: VRWM = 3.3 V Ultra low capacitance CL = 0.4 pF I/O to GND (typical) Very low clamping voltage: VCL = 8 V at IPP = 16 A (typical) Very low dynamic resistance: RDYN = 0.19 Ω (typical) TSLP-9-1 package with pad pitch 0.5 mm, optimized pad design to simplify PCB layout Pb-free and halogen free package (RoHS compliant) 1.2
•
•
• Application Examples USB 3.0, 10/100/1000 Ether.