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MAX 7000 Programmable Logic Device Family Data Sheet ■ Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest ■ Program.
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■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2)
■ 5-ns pi.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | EPM7128AE |
Altera Corporation |
Programmable Logic Device |
|
| 2 | EPM7128B |
Altera Corporation |
(EPM7000B) Programmable Logic Device |
|
| 3 | EPM7128EPLD |
Altera |
Programmable Logic Device |
|
| 4 | EPM7160E |
Altera |
Programmable Logic |
|
| 5 | EPM7160EPLD |
Altera |
High Performance 160-Macrocell Device |
|
| 6 | EPM7192E |
Altera |
Programmable Logic |
|
| 7 | EPM7000B |
Altera Corporation |
(EPM7000B) Programmable Logic Device |
|
| 8 | EPM7032 |
Altera |
Programmable Logic |
|
| 9 | EPM7032AE |
Altera Corporation |
Programmable Logic Device |
|
| 10 | EPM7032B |
Altera Corporation |
(EPM7000B) Programmable Logic Device |
|
| 11 | EPM7064 |
Altera |
Programmable Logic |
|
| 12 | EPM7064AE |
Altera Corporation |
Programmable Logic Device |
|