EM6GE16EWXC - EtronTech

EM6GE16EWXC 256M x 16 bit DDR3 Synchronous DRAM

Table 3. Ball Descriptions Symbol CK, CK# Type Input Description EM6GE16EWXC Differential Clock: CK and CK# are driven by the system clock. All SDRAM input signals are sampled on the crossing of positive edge of CK and negative edge of CK#. Output (Read) data is referenced to the crossings of CK and CK# (both directions of crossing). Clock Enable: CKE act.

Features

• JEDEC Standard Compliant
• Power supplies: VDD & VDDQ = +1.5V ± 0.075V
• Operating temperature: 0~95°C (TC)
• Supports JEDEC clock jitter specification
• Fully synchronous operation
• Fast clock rate: 667/800/933MHz
• Differential Clock, CK & CK#
• Bidirectional differential data strobe -DQS & DQS#
• 8 internal banks for concurrent operation
• 8n-bit prefetch architecture
• Internal pipeline architecture
• Precharge & active power down
• Programmable Mode & Extended Mode registers
• Additive Latency (AL): 0, CL-1, CL-2
• Programmable Burst lengths: 4, 8
• Burst type: Sequential / Interleave .