EBE21RD4AGFB - Elpida Memory

EBE21RD4AGFB 2GB Registered DDR2 SDRAM DIMM

Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 CB0 to CB7 /RAS /CAS /WE /CS0, /CS1 CKE0, CKE1 CK0 /CK0 DQS0 to DQS17, /DQS0 to /DQS17 SCL SDA SA0 to SA2 VDD VDDSPD VREF VSS ODT0, ODT1 /RESET Par_In* 2 2 www.DataSheet4U.com Function Address input Row address Column address Auto precharge Bank select address Data input/output Check bit (Data input/output) R.

Features

• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data referenced to both edges of DQS
• Posted /CAS by programmable additive latency for better co.