DS2176 - Dallas Semiconducotr

DS2176 T1 Receive Buffer

The DS2176 is a low–power CMOS device specifically designed for synchronizing receive side loop– timed T–carrier data streams with system side timing. The device has several flexible operating modes which simplify interfacing incoming data to parallel and serial TDM backplanes. The device extracts, buffers and integrates ABCD signaling; signaling updates are.

Features

§ § § § § § § § § § § § § PIN ASSIGNMENT SIGH RMSYN RCLK RSER A B C D SCHCLK SM0 SM1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD SCKLSEL SYCLK SSER SLIP SBIT8 SMSYNC SIGFRZ SFSYNC ALN FMS S/P Synchronizes loop
  –timed and system
  –timed T1 data streams Two
  –frame buffer depth; slips occur on frame boundaries Output indicates when slip occurs Buffer may be recentered externally Ideal for 1.544 to 2.048 MHz rate conversion Interfaces to parallel or serial backplanes Extracts and buffers robbed
  –bit signaling Inhibits signaling updates during alarm or slip conditions Integr.