This Schottky memory is organized in the popular 512 words by 8 bits configuration A memory enable input is provided to control the output states When the device is enabled the outputs represent the contents of the selected word When disabled the 8 outputs go to the ‘‘OFF’’ or high impedance state PROMs are shipped from the factory with lows in all locations.
Y Y
Y Y
Y Y
Advanced titanium-tungsten (Ti-W) fuses Schottky-clamped for high speed Address access 45 ns max Enable access 30 ns max Enable recovery 30 ns max PNP inputs for reduced input loading All DC and AC parameters guaranteed over temperature Low voltage TRI-SAFETM programming Open-collector outputs
Block Diagram
TL D 9715
– 1
Pin Names A0
–A8 G GND Q0
–Q7 VCC Addresses Output Enable Ground Outputs Power Supply
TRI-SAFETM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation
TL D 9715
RRD-B30M105 Printed in U S A
Connection Diagrams
Dual-In.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | DM74S472 |
National Semiconductor |
4096-Bit TTL PROM | |
2 | DM74S475 |
National Semiconductor |
4096-Bit TTL PROM | |
3 | DM74S40 |
Fairchild Semiconductor |
Dual 4-Input NAND Buffer | |
4 | DM74S04 |
National Semiconductor |
HEX INVERTING GATES | |
5 | DM74S08 |
Fairchild Semiconductor |
Quad 2-Input AND Gate | |
6 | DM74S08 |
National Semiconductor |
Quad 2-Input AND Gates | |
7 | DM74S10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate | |
8 | DM74S11 |
Fairchild Semiconductor |
Triple 3-Input AND Gate | |
9 | DM74S112 |
Fairchild Semiconductor |
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop | |
10 | DM74S132 |
National Semiconductor |
Quad 2-Input Schmitt Trigger NAND Gate | |
11 | DM74S133 |
Fairchild Semiconductor |
13-Input NAND Gate | |
12 | DM74S138 |
Fairchild Semiconductor |
Decoder/Demultiplexer |