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Pin 1 2 3 4 5 6 7 8 Name XIN/CLKIN VDD PD#/OE VSS SSCLK REFCLK SSON XOUT 3.3V voltage supply. Power-down pin. Active LOW. If PD# = 0, SSCLK and REFCLK are three-stated. Output Enable pin: Active HIGH. If OE = 1, SSCLK and REFCLK are enabled. User has the option of choosing either PD# or OE function. GND. Spread spectrum clock output. Buffered reference outp.
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Benefits
• Services most PC peripherals, networking, and consumer applications.
• Provides wide range of spread percentages for maximum EMI reduction, to meet regulatory agency Electro Magnetic Compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market.
• Eliminates the need for expensive and difficult to use higher order crystals.
• Internal PLL to generate up to 200-MHz output. Able to generate custom frequencies from an external crystal or a driven source.
• Enables fine-tuning of output clock frequency by adjusting CLoad of the crysta.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CY2509 |
Cypress Semiconductor |
(CY2509 / CY2510) Ten/Eleven Output Zero Delay Buffer |
|
| 2 | CY2510 |
Cypress Semiconductor |
(CY2509 / CY2510) Ten/Eleven Output Zero Delay Buffer |
|
| 3 | CY25100 |
Cypress Semiconductor |
Field and Factory Programmable Spread Spectrum Clock Generator |
|
| 4 | CY25103 |
Cypress Semiconductor |
Programmable Spread Spectrum Clock Generator |
|
| 5 | CY25200 |
Cypress |
Programmable Spread Spectrum Clock Generator |
|
| 6 | CY25402 |
Cypress |
Two-PLL Programmable Clock Generator |
|
| 7 | CY25403 |
Cypress |
Three-PLL Programmable Clock Generator |
|
| 8 | CY25404 |
Cypress Semiconductor |
Quad PLL Programmable Clock Generator |
|
| 9 | CY25422 |
Cypress |
Two-PLL Programmable Clock Generator |
|
| 10 | CY25423 |
Cypress |
Three-PLL Programmable Clock Generator |
|
| 11 | CY2544 |
Cypress Semiconductor |
Quad PLL Programmable Clock Generator |
|
| 12 | CY2545 |
Cypress |
Quad-PLL Programmable Spread Spectrum Clock Generator |
|