CS5821 receives three LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer. A digital phase alignment circuit can generate the sampling clock of the deserializer.
CS5821
21:3 LVDS Receiver
• Three 7-bit serial data LVDS channels and one clock LVDS channel.
• Compatible with ANSI TIA/EIA-644 LVDS standard.
• Wide serial clocking speed ranges from 31MHz to 68MHz.
• Support open-safe LVDS design.
• Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation.
• Support power-down mode.
• 5V/3.3V tolerant data input.
• Single 3.3V supply operation.
• CMOS low power consumption.
• Functional compatible with DS90CF364 and SN75LVDS86.
• Available in 48-pin TSSOP package.
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DataS.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CS5820 |
Myson Technology |
21:3 LVDS Transmitter | |
2 | CS5823 |
Myson Technology |
TMDS Receiver | |
3 | CS5824 |
Myson Technology |
28:4 LVDS Transmitter | |
4 | CS5825 |
Myson Technology |
28:4 LVDS Receiver | |
5 | CS5826 |
Myson Technology |
Dual Pixel LVDS Display Interface (LDI) Transmitter | |
6 | CS5828 |
Myson Technology |
28:4 LVDS Transmitter | |
7 | CS5800-04 |
TOKYO ELECTRONIC |
3CCD Color Camera Operation Manual | |
8 | CS5800P-04 |
TOKYO ELECTRONIC |
3CCD Color Camera Operation Manual | |
9 | CS5801 |
CapSton |
HDMI-2.0b to DisplayPort-1.4 Converter | |
10 | CS5801T |
Chipstar |
Battery protection | |
11 | CS5805S |
Chipstar |
LI+ Charger Front-End Protection | |
12 | CS5841 |
Myson Century |
LCD Panel Timing Controller |