CR16MCS5 - National Semiconductor

CR16MCS5 Family of 16-bit CAN-enabled CompactRISC Microcontrollers

plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed .

Features

and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com- Block Diagram Fast Clk Slow Clk
* CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit Core Bus Peripheral Bus Controller 64k-Byte Flash Program Memory 3k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Peripheral Bus I/O µWire/SPI 2x USART ACCESS bus 4x VTU 2x MFT 12-ch 8-bit A/D MIWU 2 Analog Comparato.