CLC5903 - National Semiconductor

CLC5903 Dual Digital Tuner / AGC

The CLC5903 block diagram is shown in Figure 2. The CLC5903 contains two identical digital down-conversion (DDC) circuits. Each DDC accepts an independently clocked 14-bit sample at up to 78MSPS, down converts from a selected carrier frequency to baseband, decimates the signal rate by a programmable factor ranging from 32 to 16384, provides channel filtering.

Features

„ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ 78MSPS Operation Low Power, 145mW/channel, 52 MHz, Dec=192 Two Independent Channels with 14-bit inputs Serial Daisy-chain Mode for quad receivers Greater than 100 dB image rejection Greater than 100 dB spurious free dynamic range 0.02 Hz tuning resolution User Programmable AGC with enhanced Power Detector Channel Filters include a Fourth Order CIC followed by 21-tap and 63-tap Symmetric FIRs FIR filters process 21-bit Data with 16-bit Programmable Coefficients Two independent FIR coefficient memories which can be routed to either or both channels. Flexible .