CLA60000 - Zarlink Semiconductor

CLA60000 Channel Less CMOS Gate Arrays

Th e CLA60000 gate arra y f amily i s Zarlink Semiconductor’s fifth-generation CMOS gate array product. These arrays allow even higher integration densities at enhanced system clock rates as need for many of today’s system applications. The largest array in the family at 110K gates offers a tenfold increase in raw gate availability then channelled gate arrays.

Features

have been incorporated such as analog functionality, slew rate output control, and intermediate I/O buffering for optimum data transfer through peripheral cells. Also, the low-power characteristics of Zarlink Semiconductor CMOS processing have been incorporated in these arrays, easing the thermal management problems associated with complex designs of 20,000 gates and above. Features
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• Channel less arrays to 110,000 gates 1.4 micron dual layer metal silicon CMOS process Typical Gate Delays of 700ps (NAND2) Comprehensive cell library including microcells, macrocells, and paracells.