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The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock output pair, Y0 and Y0, and one single-ended LVCMOS output, Y1. It is specifically designed for driving 50-Ω transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions. The C.
•1 Distributes One Differential Clock Input to One LVPECL Differential Clock Output and One LVCMOS Single-Ended Output
• Programmable Output Divider for Both LVPECL and LVCMOS Outputs
• 1.6-ns Output Skew Between LVCMOS and LVPECL Transitions Minimizing Noise
• 3.3-V Power Supply (2.5-V Functional)
• Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
• Differential Input Stage for Wide Common-Mode
Range Also Provides VBB Bias Voltage Output for Single-Ended Input Signals
• Receiver Input Threshold ±75 mV
• 16-Pin VQFN Package (3.00 mm × 3.00 mm)
3 Description
The CDCM1802 clock driver dis.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CDCM1804 |
Texas Instruments |
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER |
|
| 2 | CDCM61001 |
Texas Instruments |
Low-Jitter Clock Generator |
|
| 3 | CDCM61002 |
Texas Instruments |
Low-Jitter Clock Generator |
|
| 4 | CDCM61004 |
Texas Instruments |
Low-Jitter Clock Generator |
|
| 5 | CDCM6208 |
Texas Instruments |
Jitter Cleaner |
|
| 6 | CDCM6208V1F |
Texas Instruments |
Jitter Cleaner |
|
| 7 | CDCM6208V2G |
Texas Instruments |
Jitter Cleaner |
|
| 8 | CDCM7005 |
Texas Instruments |
3.3-V High Performance Clock Synchronizer and Jitter Cleaner |
|
| 9 | CDCM7005-SP |
Texas Instruments |
Clock Synchronizer and Jitter Cleaner |
|
| 10 | CDCM9102 |
Texas Instruments |
Low-Noise Two-Channel 100-MHz Clock Generator |
|
| 11 | CDC-Z137 |
Aiwa |
FM / AM CD Player |
|
| 12 | CDC1104 |
Texas Instruments |
1 to 4 Configurable Clock Buffer |
|