CD74HC40103-Q1 - Texas Instruments

CD74HC40103-Q1 8-STAGE SYNCHRONOUS DOWN COUNTER

ordering information CD74HC40103-Q1 HIGH-SPEED CMOS LOGIC 8-STAGE SYNCHRONOUS DOWN COUNTER SCLS547A − OCTOBER 2003 − REVISED APRIL 2008 D VCC Voltage = 2 V to 6 V D High Noise Immunity NIL or NIH = 30% of VCC, VCC = 5 V M PACKAGE (TOP VIEW) CP MR TE P0 P1 P2 P3 GND 1 2 3 4 5 6 7 8 16 VCC 15 PE (SYNC) 14 TC 13 P7 12 P6 11 P5 10 P4 9 PL (ASYNC) The CD74HC.

Features

isabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count (TC) output are active-low logic. In normal operation, the counter is decremented by one count on each positive transition of the clock (CP) output. Counting is inhibited when the terminal enable (TE) input is high. TC goes low when the count reaches zero, if TE is low, and remains low for one full clock period. When the synchronous preset enable (PE) input is low, data at the P0−P7 inputs are clocked into the counte.