CD74AC112 - Texas Instruments

CD74AC112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

ordering information The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outpu.

Features

rements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP
  – E Tube CD74AC112E CD74AC112E
  –55°C to 125°C SOIC
  – M Tube CD74AC112M Tape and reel CD74AC112M96 AC112M .