CD54HC163 - Texas Instruments

CD54HC163 High-Speed CMOS Logic Presettable Counters

Two count enables, PE and TE, in each counter are provided for n-bit cascading. In all counters reset action occurs regardless of the level of the SPE, PE and TE inputs (and the clock input, CP, in the ’HC161 and ’HCT161 types). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it will return to the normal .

Features

• ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset
• ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset
• Synchronous Counting and Loading
• Two Count Enable Inputs for n-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2V to 6V Operation - Hi.