Pin # 1 Symbol CE Pin Description Chip Enable pin Chi in (1) ( ) The chip is enabled if a voltage g which is equal q to or greater g than 0.9 V is applied ( ) The (2) Th chip hi is i disabled di bl d if a voltage l which hi h is i less l than h 0.3 V is i applied li d (3) The chip will be enabled if it is left floating Output voltage monitor pin, also the p.
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5 1 SOT23−5 (TSOP−5, SC59−5) SN SUFFIX CASE 483
PIN CONNECTIONS AND MARKING DIAGRAM
CE OUT NC 1 xxxYW 2 3 5 LX
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Extremely Low Start−Up Voltage of 0.8 V Operation Down to Less than 0.3 V High Efficiency 85% (Vin = 2.0 V, VOUT = 3.0 V, 70 mA) Low Operating Current of 30 mA (VOUT = 1.9 V) Output Voltage Accuracy ± 2.5% Low Converter Ripple with Typical 30 mV Only Three External Components Are Required Chip Enable Power Down Capability for Extended Battery Life Micro Miniature Thin SOT−23−5 Packages Cellular Telephones Pagers Personal Digital .
Pin # 1 Symbol CE Pin Description Chip Enable pin Chi in (1) ( ) The chip is enabled if a voltage g which is equal q to.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | CD54-390LB |
Sumida |
Ind / Wirewound | |
2 | CD54-390LC |
Sumida |
Ind / Wirewound | |
3 | CD54 |
Sumida |
Ind / Wirewound | |
4 | CD54573CS |
HUAJING |
Tuner Band Switcher | |
5 | CD54AC00 |
Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-NAND GATES | |
6 | CD54AC02 |
Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-NOR GATES | |
7 | CD54AC04 |
Texas Instruments |
Hex Inverters | |
8 | CD54AC05 |
Texas Instruments |
HEX INVERTERS | |
9 | CD54AC08 |
Texas Instruments |
QUADRUPLE 2-INPUT POSITIVE-AND GATES | |
10 | CD54AC109 |
Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS | |
11 | CD54AC112 |
Texas Instruments |
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS | |
12 | CD54AC138 |
Texas Instruments |
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS |