CD4076BMS - Intersil Corporation

CD4076BMS CMOS 4 -Bit D-Type Registers

of ‘B’ Series CMOS Devices” OUTPUT DISABLE Functional Diagram DATA INPUT DISABLE G1 9 14 D1 13 D2 12 4D - TYPE FLIP-FLOPS WITH AND-OR LOGIC 4 Q2 5 10 G2 CLOCK 7 1 OUTPUT DISABLE M 2 3 Q1 N Description CD4076BMS types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry.

Features

• High Voltage Type (20V Rating)
• Three State Outputs
• Input Disabled Without Gating the Clock
• Gated Output Control Lines for Enabling or Disabling the Outputs
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Descriptio.