Recherchez avec le numéro de pièce ainsi que le fabricant ou la description
of ‘B’ Series CMOS Devices” Q2 1 Q2 2 CLOCK 2 3 RESET 2 4 K2 5 J2 6 SET 2 7 VSS 8 16 VDD 15 Q1 14 Q1 13 CLOCK 1 12 RESET 1 11 K1 10 J1 9 SET 1 Functional Diagram SET 1 9 VDD 16 J1 10 K1 11 CLOCK1 13 F/F1 15 Q1 14 Q1 Applications • Registers, Counters, Control Circuits RESET1 12 SET2 J2 K2 7 6 5 3 F/F2 2 Q2 1 Q2 Description CD4027BMS is a single monoli.
• High Voltage Type (20V Rating)
• Set - Reset Capability
• Static Flip-Flop Operation - Retains State Indefinitely with Clock Level Either “High” or “Low”
• Medium Speed Operation - 16MHz (typ.) Clock Toggle Rate at 10V
• Standardized Symmetrical Output Characteristics
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Package-Temperature Range; - 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentati.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CD4027BM |
National Semiconductor |
Dual J-K Master/Slave Flip-Flop |
|
| 2 | CD4027BM |
Texas Instruments |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 3 | CD4027B |
RCA |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 4 | CD4027B |
Texas Instruments |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 5 | CD4027BC |
National Semiconductor |
Dual J-K Master/Slave Flip-Flop |
|
| 6 | CD4027BC |
Fairchild Semiconductor |
Dual J-K Master/Slave Flip-Flop |
|
| 7 | CD4027BCM |
Fairchild Semiconductor |
Dual J-K Master/Slave Flip-Flop |
|
| 8 | CD4027BCN |
Fairchild Semiconductor |
Dual J-K Master/Slave Flip-Flop |
|
| 9 | CD4027BE |
Texas Instruments |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 10 | CD4027BF |
Texas Instruments |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 11 | CD4027BF3A |
Texas Instruments |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|
| 12 | CD4027A |
RCA |
CMOS DUAL J-K MASTER-SLAVER FLIP-FLOP |
|