The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is fanned-out to nine identical differential outputs. An Enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q ¯ outputs HIGH. The AZ100LVE111E provides a VBB output for single-ended use or a DC bias.
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• Operating Range of 3.0V to 5.5V Low Skew Guaranteed Skew Spec Differential Design Enable VBB Output 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor MC10E111 & MC100E111 PACKAGE
PLCC 28
PACKAGE AVAILABILITY PART NO. AZ10LVE111EFN AZ100LVE111EFN MARKING
AZ10 LVE111E
The AZ10/100LVE111E is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The IN signal is.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | AZ10LVE111 |
Arizona Microtek |
ECL/PECL 1:9 Differential Clock Driver | |
2 | AZ10LVE111 |
Arizona Microtek |
ECL/PECL 1:9 Differential Clock Driver | |
3 | AZ10LVEL11 |
Arizona Microtek |
ECL/PECL 1:2 Differential Fanout Buffer | |
4 | AZ10LVEL16 |
Arizona Microtek |
ECL/PECL Differential Receiver | |
5 | AZ10LVEL16VS |
Arizona Microtek |
ECL/PECL Differential Receiver | |
6 | AZ10LVEL32 |
Arizona Microtek |
ECL/PECL / 2 Divider | |
7 | AZ10LVEL33 |
Arizona Microtek |
ECL/PECL / 4 Divider | |
8 | AZ100E111 |
Arizona |
1:9 Differential Clock Driver | |
9 | AZ100E116 |
Arizona Microtek |
ECL/PECL Quint Differential Line Receiver | |
10 | AZ100E131 |
Arizona Microtek |
ECL/PECL 4-bit D Flip-Flop | |
11 | AZ100E142 |
Arizona Microtek |
ECL/PECL 9-bit Shift Register | |
12 | AZ100EL01 |
Arizona Microtek |
ECL/PECL 4-Input OR/NOR |