ATLV5 - ATMEL Corporation

ATLV5 Ultra Low Voltage Gate Arrays

The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility. The arrays utilize an enhanced channelless architecture which results in greater than 50 percent usable gates. Atmel's flexible design system uses industry design standards and is compatible with .

Features

Specifically Designed for Battery Powered Applications 1.0 - 3.0 Volts and will Operate from 0.7 to 5.5 Volts
• Static Current Drain of <75 nA at 1.0 Volts
• 200 MHz Maximum Toggle Frequency for Flip Flop at 1.5 Volts
• 1.0 µ Drawn Gate Length CMOS Gate Arrays
• All Package Styles Offered Including TQFP and TAB
• Improved Product Testability Using Serial Scan, Boundary Scan, www.datasheet4u.com and JTAG
• Second Source Existing ASIC Design in Atmel's ATLV via Design Translation. Improved Performance and Lower Cost
• Description The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-leve.