ASM4SSTVF32852 - Alliance Semiconductor Corporation

ASM4SSTVF32852 DDR 24-Bit to 48-Bit Registered Buffer

The 24-Bit to 48-Bit ASM4SSTVF32852 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels except for the LVCMOS RESETB input. Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficie.

Features

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 Differential clock signals. Supports SSTL_2 class II specifications on inputs and outputs. Low voltage operation.
 VDD = 2.3V to 2.7V. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic “Low” level during power-up. In the DDR DIMM application, RESETB is specified to be asynchronous with respect to CLK/CLKB. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic “Low” level quickly rel.