AN644 - Maxim Integrated Products

AN644 QuickChip Design Example 2 Low Power Silicon BJT LNA for 1.9GHz

ASICs Application Note 644: Mar 17, 2000 QuickChip Design Example 2 Low Power Silicon BJT LNA for 1.9GHz 1998 IEEE. Reprinted, with permission, from 1998 IEEE Microwave and Guided Wave Letters, Vol. 3, No. 3, pp. 136-137 Abstract A two-stage 1.9GHz monolithic low-noise amplifier (LNA) with a measured noise figure of 2.3dB and an associated gain of 15dB wa.

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requency performance of stateof-the-art silicon bipolar processes are continuously improving lowcost semi-custom arrays with a limited choice of components provide a reasonable solution for RF applications. In order to demonstrate such a solution, we present in this letter a very low-power monolithic 1.9GHz silicon LNA which draws a total current of 1.75mA including bias circuit. II. Circuit Design A schematic of the two-stage LNA is shown in Fig. 1. The circuit employs a high-gain common-emitter stage (Q1-RL) and a emitter-follower output stage (Q2-Q3). This approach eliminates the need for c.