9DB836 - Renesas

9DB836 8-Output 3.3V HCSL PCIe Buffer

The 9DB836 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1–3 in zero-delay mode and PCIe Gen1–4 in fanout mode. The 9DB836 is a pin-compatible upgrade to the 9DB833 and 9DB834 with a Safe Power Sequence (SPS) clock input. Typical Applications ▪ Riser cards ▪ Storage ▪ Networking ▪ JBOD Output Features ▪ Eight 0.7V current-mode .

Features

▪ Eight 0.7V current-mode differential HCSL output pairs ▪ Supports zero delay buffer (ZDB) mode and fanout mode ▪ Selectable bandwidth for zero delay mode ▪ 50
  –110 MHz operation in PLL mode ▪ 5
  –166 MHz operation in Bypass mode Features ▪ SPS internal receiver bias network keeps input clock parked when input is floating ▪ Supports both 85Ω and 100Ω output impedance with appropriate resistor selection ▪ OE# pins default to controlling outputs ▪ PLL or Bypass mode; PLL can dejitter incoming clock ▪ Selectable PLL bandwidth; minimizes jitter peaking in downstream PLLs ▪ Spread spectrum compatibl.