74LVT74 - NXP

74LVT74 3.3V Dual D-type flip-flop

The 74LVT74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs .

Features

not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output. tPLH tPHL CIN ICC 3.1 3.6 3 0.5 ns pF mA PIN CONFIGURATION RD0 D0 CP0 SD0 Q0 Q0 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RD1 D1 CP1 SD1 Q1 Q1 PIN DESCRIPTION PIN NUMBER 2, 12 3, 11 4, 10 1, 13 5, 6, 8, 9 SF00045 SYMBOL D0, D1 CP0, CP1 SD0, SD1 RD0, RD1 Qn, Qn NAME AND FUNCTION Data inputs Clock inputs (active rising edge) Set inputs (active LOW) Reset inputs (active LOW) Data outputs LOGIC SYMBOL (IEE.