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The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LO.
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74LVC1G175-Q100 - nexperia
The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D).
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | 74LVC1G175 |
nexperia |
Single D-type flip-flop |
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| 2 | 74LVC1G175 |
NXP Semiconductors |
Single D-type flip-flop |
|
| 3 | 74LVC1G17 |
NXP |
Single Schmitt-trigger buffer |
|
| 4 | 74LVC1G17 |
Diodes |
SINGLE SCHMITT-TRIGGER BUFFER |
|
| 5 | 74LVC1G17 |
nexperia |
Single Schmitt trigger buffer |
|
| 6 | 74LVC1G17-Q100 |
nexperia |
Single Schmitt trigger buffer |
|
| 7 | 74LVC1G10 |
Diodes |
SINGLE 3 INPUT POSITIVE NAND GATE |
|
| 8 | 74LVC1G10 |
nexperia |
Single 3-input NAND gate |
|
| 9 | 74LVC1G10-Q100 |
nexperia |
Single 3-input NAND gate |
|
| 10 | 74LVC1G11 |
NXP |
Single 3-input AND gate |
|
| 11 | 74LVC1G11 |
Diodes |
SINGLE 3 INPUT POSITIVE AND GATE |
|
| 12 | 74LVC1G11 |
nexperia |
Single 3-input AND gate |
|