74LVC1G07 The 74LVC1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 and 5 V environment. Schmitt trigger action at the input makes the circuit toleran.
• Wide supply voltage range from 1.65 to 5.5 V
• High noise immunity
• Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
• 24 mA output drive (VCC = 3.0 V)
• CMOS low power consumption
• Latch-up performance ≤250 mA
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• SOT353 package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. SYMBOL tPLZ/tPZL CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency .
The 74LVC1G07 is a single buffer gate with an open-drain output. The device is designed for operation with a power suppl.
The 74LVC1G07 is a single buffer with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This fea.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LVC1G00 |
Diodes |
SINGLE 2 INPUT POSITIVE NAND GATE | |
2 | 74LVC1G00 |
nexperia |
Single 2-input NAND gate | |
3 | 74LVC1G00-Q100 |
nexperia |
Single 2-input NAND gate | |
4 | 74LVC1G02 |
Diodes |
SINGLE 2 INPUT POSITIVE NOR GATE | |
5 | 74LVC1G02 |
nexperia |
Single 2-input NOR gate | |
6 | 74LVC1G02-Q100 |
nexperia |
Single 2-input NOR gate | |
7 | 74LVC1G04 |
nexperia |
Single inverter | |
8 | 74LVC1G04 |
Diodes |
SINGLE INVERTER | |
9 | 74LVC1G04-Q100 |
nexperia |
Single inverter | |
10 | 74LVC1G06 |
Diodes |
SINGLE INVERTER BUFFER/DRIVER | |
11 | 74LVC1G06 |
nexperia |
Inverter | |
12 | 74LVC1G06-Q100 |
nexperia |
Inverter |