The LS83A adds two 4-bit binary words (A plus B) plus the incoming carry. The binary sum appears on the sum outputs (∑1 – ∑4) and outgoing carry (C4) outputs. C0 + (A1+B1)+2(A2+B2)+4(A3+B3)+8(A4+B4) = ∑1+2∑2+4∑3+8∑4+16C4 Where: (+) = plus Due to the symmetry of the binary add function the LS83A can be used with either all inputs and outputs active HIGH (posi.
standard corner power pins.
CONNECTION DIAGRAM DIP (TOP VIEW)
B4 Σ4 C4 C0 GND B1 A1 Σ1 16 15 14 13 12 11 10 9
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
12 A4 Σ3
3 4 56 A3 B3 VCC Σ2
78 B2 A2
PIN NAMES
LOADING (Note a)
HIGH
LOW
A1
– A4 B1
– B4
C0 Σ1
– Σ4 C4
Operand A Inputs Operand B Inputs Carry Input Sum Outputs (Note b) Carry Output (Note b)
1.0 U.L. 1.0 U.L. 0.5 U.L. 10 U.L. 10 U.L.
0.5 U.L. 0.5 U.L. 0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74LS83 |
Fairchild Semiconductor |
4-Bit Binary Adder | |
2 | 74LS83 |
Motorola |
4-BIT BINARY FULL ADDER | |
3 | 74LS848 |
Motorola |
8-INPUT PRIORITY ENCODERS | |
4 | 74LS85 |
ON Semiconductor |
LOW POWER SCHOTTKY | |
5 | 74LS85 |
Fairchild Semiconductor |
4-Bit Magnitude Comparator | |
6 | 74LS86 |
System Logic Semiconductor |
Quad 2-Input Exclusive OR Gate | |
7 | 74LS86 |
Fairchild Semiconductor |
Quad 2-Input Exclusive-OR Gate | |
8 | 74LS86 |
Hitachi Semiconductor |
Quadruple 2-input Exclusive-OR Gates | |
9 | 74LS86A |
Texas Instruments |
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE | |
10 | 74LS89 |
Fairchild Semiconductor |
64-Bit RAM | |
11 | 74LS89 |
Signetics |
64-Bit RAM | |
12 | 74LS00 |
Fairchild Semiconductor |
Quad 2-Input NAND Gate |