74LS42 - National Semiconductor

74LS42 Decimal Decoders

These BCD-to-decimal decoders consist of eight inverters and ten four-input NAND gates The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates Full decoding of input logic ensures that all outputs remain off for all invalid (10–15) input conditions Features Y Y Y Y Diode clamped inputs Also for applications as .

Features

Y Y Y Y Diode clamped inputs Also for applications as 4-line-to-16-line decoders 3line-to-8-line decoders All outputs are high for invalid input conditions Alternate Military Aerospace device (54LS42) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package Function Table No 0 1 2 3 4 5 6 7 8 9 I N V A L I D BCD Inputs D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H 0 L H H H H 1 H L H H H 2 Decimal Outputs 3 4 5 6 7 8 9 H H H H H.