The 74HC273; 74HCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of clock and d.
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• Input levels:
• For 74HC273: CMOS level
• For 74HCT273: TTL level
• Common clock and master reset
• Eight positive edge-triggered D-type flip-flops
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74HC273 |
Texas Instruments |
Octal D-Type Flip-Flops | |
2 | 74HC273 |
NXP |
Octal D-type flip-flop | |
3 | 74HC273 |
nexperia |
Octal D-type flip-flop | |
4 | 74HC273-Q100 |
NXP |
Octal D-type flip-flop | |
5 | 74HC273-Q100 |
nexperia |
Octal D-type flip-flop | |
6 | 74HC273A |
ON Semiconductor |
Octal D Flip-Flop | |
7 | 74HC273BQ |
nexperia |
Octal D-type flip-flop | |
8 | 74HC273D |
Toshiba |
Octal D-Type Flip-Flop | |
9 | 74HC273D |
nexperia |
Octal D-type flip-flop | |
10 | 74HC273DB |
nexperia |
Octal D-type flip-flop | |
11 | 74HC27 |
Texas Instruments |
Triple 3-Input NOR Gates | |
12 | 74HC27 |
nexperia |
Triple 3-input NOR gate |