74HC109 - nexperia

74HC109 Dual JK flip-flop

The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as desc.

Features

• J and K inputs for easy D-type flip-flop
• Toggle flip-flop or "do nothing" mode
• Wide supply voltage range:
• For 74HC109: from 2.0 V to 6.0 V
• For 74HCT109: from 4.5 V to 5.5 V
• CMOS low power dissipation
• High noise immunity
• Input levels:
• For 74HC109: CMOS level
• For 74HCT109: TTL level
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• 74HC109 complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• 74HCT109 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exc.