The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G34 is composed of two buffers with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF cir.
Advanced Ultra Low Power (AUP) CMOS
Supply Voltage Range from 0.8V to 3.6V
±4mA Output Drive at 3.0V
Low Static Power Consumption
ICC < 0.9µA
Low Dynamic Power Consumption
CPD = 6pF Typical at 3.6V
Schmitt Trigger Action at All Inputs Make the Circuit Tolerant for
Slower Input Rise and Fall Time. The Hysteresis is Typically 250mV at VCC = 3.0V
IOFF Supports Partial-Power-Down Mode Operation
ESD Protection per JESD 22
Exceeds 200-V Machine Model (A115)
Exceeds 2000-V Human Body Model (A114)
Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 100mA per JESD 78.
The 74AUP2G34 is a dual buffer. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AUP2G32 |
Diodes |
DUAL OR GATE | |
2 | 74AUP2G32 |
NXP |
Low-power Dual 2-input OR Gate | |
3 | 74AUP2G32 |
nexperia |
Low-power dual 2-input OR gate | |
4 | 74AUP2G3404 |
Diodes |
BUFFER AND INVERTER | |
5 | 74AUP2G3404 |
nexperia |
Low-power buffer and inverter | |
6 | 74AUP2G3407 |
nexperia |
Low-power single buffer | |
7 | 74AUP2G38 |
NXP |
Low Power Dual 2-Input NAND Gate | |
8 | 74AUP2G38 |
nexperia |
Low-power dual 2-input NAND gate | |
9 | 74AUP2G00 |
NXP |
Low-power dual 2-input NAND gate | |
10 | 74AUP2G00 |
Diodes |
DUAL NAND GATE | |
11 | 74AUP2G00 |
nexperia |
Low-power dual 2-input NAND gate | |
12 | 74AUP2G00-Q100 |
nexperia |
Low-power dual 2-input NAND gate |