The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD)..
• Automotive product qualification in accordance with AEC-Q100 (Grade 1)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accept voltages higher than VCC
• Input levels:
• For 74AHC74-Q100: CMOS level
• For 74AHCT74-Q100: TTL level
• ESD protection:
• MIL-STD-883, method 3015 exceeds 2000 V
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
• Multiple package options
• DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder jo.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AHCT74 |
NXP |
Dual D-type flip-flop | |
2 | 74AHCT74 |
nexperia |
Dual D-type flip-flop | |
3 | 74AHCT74BQ |
nexperia |
Dual D-type flip-flop | |
4 | 74AHCT74D |
nexperia |
Dual D-type flip-flop | |
5 | 74AHCT74PW |
nexperia |
Dual D-type flip-flop | |
6 | 74AHCT00 |
NXP |
Quad 2-input NAND gate | |
7 | 74AHCT00 |
Diodes |
QUADRUPLE 2-INPUT NAND GATES | |
8 | 74AHCT00 |
nexperia |
Quad 2-input NAND gate | |
9 | 74AHCT00-Q100 |
nexperia |
Quad 2-input NAND gate | |
10 | 74AHCT00BQ |
nexperia |
Quad 2-input NAND gate | |
11 | 74AHCT00D |
nexperia |
Quad 2-input NAND gate | |
12 | 74AHCT00PW |
nexperia |
Quad 2-input NAND gate |