The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-input OR function. FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level. nB L H L H OUTPUT nY H L L L QU.
• ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V
• Balanced propagation delays
• All inputs have Schmitt-trigger actions
• Inputs accepts voltages higher than VCC
• For AHC only: operates with CMOS input levels
• For AHCT only: operates with TTL input levels
• Specified from −40 to +85 and +125 °C. DESCRIPTION The 74AHC/AHCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT02 provides the Quad 2-i.
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It .
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 74AHCT00 |
NXP |
Quad 2-input NAND gate | |
2 | 74AHCT00 |
Diodes |
QUADRUPLE 2-INPUT NAND GATES | |
3 | 74AHCT00 |
nexperia |
Quad 2-input NAND gate | |
4 | 74AHCT00-Q100 |
nexperia |
Quad 2-input NAND gate | |
5 | 74AHCT00BQ |
nexperia |
Quad 2-input NAND gate | |
6 | 74AHCT00D |
nexperia |
Quad 2-input NAND gate | |
7 | 74AHCT00PW |
nexperia |
Quad 2-input NAND gate | |
8 | 74AHCT00S14 |
Diodes |
QUADRUPLE 2-INPUT NAND GATES | |
9 | 74AHCT00T14 |
Diodes |
QUADRUPLE 2-INPUT NAND GATES | |
10 | 74AHCT02-Q100 |
nexperia |
Quad 2-input NOR gate | |
11 | 74AHCT02BQ |
nexperia |
Quad 2-input NOR gate | |
12 | 74AHCT02D |
nexperia |
Quad 2-input NOR gate |