ordering information These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level. The ’1.
15 2 A2 8 14 1 9 10 11 12 13 B5 GND 4 NC NC A VCC 9 NC A1 5 GND 4 NC NC A0 VCC 0 E0 NC − No internal connection TYPE ’147 ’148 ’LS147 ’LS148 TYPICAL DATA DELAY 10 ns 10 ns 15 ns 15 ns TYPICAL POWER DISSIPATION 225 mW 190 mW 60 mW 60 mW NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA.
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54 / 74LS148 are Priority Encoder.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 7414 |
Texas Instruments |
Hex Schmitt-Trigger Inverter | |
2 | 7414 |
ON Semiconductor |
Dual Gate/Hex Inverter | |
3 | 74141 |
National Semiconductor |
1-of-10 Decoder/Driver | |
4 | 74145N |
ETC |
BCD-to-DECIMAL Decoders/Drivers | |
5 | 74148 |
Texas Instruments |
Priority Encoder | |
6 | 74148 |
National Semiconductor |
8-3 Line Priority Encoder | |
7 | 74148 |
Motorola |
PRIORITY ENCODERS | |
8 | 7410 |
National Semiconductor |
Triple 3 Input NAND Gates | |
9 | 7410 |
Philips |
Triple 3-input NAND gate | |
10 | 74107 |
STMicroelectronics |
DUAL J-K FLIP-FLOP | |
11 | 74109 |
Texas Instruments |
Dual J-K Positive-Edge-Triggered Flip-Flops | |
12 | 7411 |
Fairchild Semiconductor |
Triple 3 Input AND Gate |