54LS373 - Motorola

54LS373 OCTAL TRANSPARENT LATCH

OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is la.

Features

red D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES D0
  – D7 LE CP OE O0
  – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) LOADING (Note a) HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 65 (25) U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 15 (7.5) U.L. NOTES: a) 1 TTL Units Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 25.