54LS256 - Motorola

54LS256 DUAL 4-BIT ADDRESSABLE LATCH

DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs (A0, A1), an active LOW Enable input (E) and an active LOW Clear input (CL). Each latch has a Data input (D) and four outputs (Q0 – Q3). When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs (Q0 – Q3).

Features

put Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC CL E Db Q3b Q2b Q1b Q0b 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 12 A0 A1 3 4 56 78 Da Q0a Q1a Q2a Q3a GND PIN NAMES LOADING (Note a) HIGH LOW A0, A1 Da, Db E Address Inputs Data Inputs Enable Input (Active LOW) 0.5 U.L. 0.5 U.L. 1.0 U.L. 0.25 U.L. 0.25 U.L. 0.5 U.L. CL Clear Input (Active LOW) 0.5 U.L. 0.25 U.L. Q0a
  – Q3a, Q0b
  – Q3b Parallel Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L. NOTES: a) 1 TTL Unit .