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This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B in positive logic. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CD74HCT00M SOIC (14) 8.65 mm × 3.90 mm CD74HCT00E PDIP (14) 19.30 mm × 6.40 mm CD54HCT00J CDIP (14) 19.94 mm × 7.62 mm (1) For all available packages, see the or.
• LSTTL input logic compatible
– VIL(max) = 0.8 V, VIH(min) = 2 V
• CMOS input logic compatible
– II ≤ 1 µA at VOL, VOH
• Buffered inputs
• 4.5 V to 5.5 V operation
• Wide operating temperature range:
–55°C to +125°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL
logic ICs
2 Applications
• Alarm / tamper detect circuit
• S-R latch
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
7
3 Description
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A
● B in positive logic.
Device Information
PART NUMBER
P.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | 54HCT04 |
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| 2 | 54HCT166 |
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| 3 | 54HCT173 |
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| 4 | 54HCT240 |
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| 5 | 54HCT241 |
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| 6 | 54HCT244 |
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| 7 | 54HCT244 |
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High-Speed CMOS Logic Octal Buffer/Line Drivers |
|
| 8 | 54HCT245 |
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Rad-hard high speed 2 to 6V CMOS logic |
|
| 9 | 54HCT245 |
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| 10 | 54HCT30 |
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|
| 11 | 54HCT32 |
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|
| 12 | 54HCT367 |
Texas Instruments |
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|