The ’FCT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the correspondin.
n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’FCT273 for master reset version n See ’FCT373 for transparent latch version n See ’FCT374 for TRI-STATE® version n TTL input and output level compatible n CMOS power consumption n Output sink capability of 32 mA, source capability of 12 mA n Standard Microcircuit Drawing (SMD) 5962-8762701 Ordering Code Military 54FCT377DMQB 54FCT377FMQB 54FCT377LMQB Connection Diagram Package Number J20A W20A E20A Pin Assignment for DIP and Cerpack Package Description 20-Lead.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | 54FCT374 |
National Semiconductor |
Octal D-Type Flip-Flop | |
2 | 54FCT241 |
National Semiconductor |
Octal Buffer/Line Driver | |
3 | 54FCT244 |
National Semiconductor |
Octal Buffer/Line Driver | |
4 | 54FCT244 |
PYRAMID |
OCTAL BUFFER/LINE DRIVER | |
5 | 54FCT244 |
IDT |
FAST CMOS OCTAL BUFFER/LINE DRIVER | |
6 | 54FCT244A |
IDT |
FAST CMOS OCTAL BUFFER/LINE DRIVER | |
7 | 54FCT244C |
IDT |
FAST CMOS OCTAL BUFFER/LINE DRIVER | |
8 | 54FCT245 |
PYRAMID |
OCTAL TRANSCEIVER | |
9 | 54FCT245 |
National Semiconductor |
Octal Bidirectional Transceiver | |
10 | 54FCT245AT |
Renesas |
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVER | |
11 | 54FCT245AT |
IDT |
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVER | |
12 | 54FCT245CT |
IDT |
FAST CMOS OCTAL BIDIRECTIONAL TRANSCEIVER |