17S50A - Xilinx

17S50A Spartan-II/Spartan-IIE Family OTP Configuration PROMs

Pins not listed are "no connects." Table 1: XC17S00A PROM Pinouts 8-pin PDIP (PD8) and VOIC/TSOP (VO8) 1 Pin Name DATA 20-pin SOIC (SO20) 1 44-pin VQFP (VQ44) 40 Pin Description Data output, High-Z state when either CE or OE are inactive. During programming, the DATA pin is I/O. Note that OE can be programmed to be either active High or active Low. Each .

Features

Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan-II/Spartan-IIE FPGA devices
• Simple interface to the Spartan device
• Programmable reset polarity (active High or active Low)
• Low-power CMOS floating gate process www.DataSheet4U.com
• 3.3V PROM
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• Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages. Programming support by leading programmer manufacturers. Design support using the Xilinx Alliance and Foundation series software packages. Guaranteed 20-year life data retention Introduct.