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K7K3236U2C |
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| Part Number | K7K3236U2C |
| Manufacturer | Samsung semiconductor |
| Description | Input Clock Q Valid output Output Echo Clock DLL Disable Address Inputs Data Inputs Outputs Read, Write Control Pin, Read active when high Synchronous Load Pin, bus Cycle sequence is to be defined whe... |
| Features |
• 1.8V+0.1V/-0.1V Power Supply. • DLL circuitry for wide output data valid window and future freguency scaling. • I/O Supply Voltage 1.5V+0.1V/-0.1V • Pipelined, double-data rate operation. • Common data input/output bus . • HSTL I/O • Full data coherency, providing most current data. • Synchronous pipeline read with self timed late write. • Read latency : 2.5 clock cycles • Registered address, control and data input/output. • DDR(Double Data Rate) Interface on read and write ports. • Fixed 2-bit burst for both read and write operation. • Clock-stop supports to reduce current. • Two input cloc... |
| Document |
 K7K3236U2C Data Sheet
PDF 439.34KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | K7K3236T2C |
Samsung semiconductor |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
|
| 2 | K7K3218T2C |
Samsung semiconductor |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
|
| 3 | K7K3218U2C |
Samsung semiconductor |
1Mx36 & 2Mx18 DDRII CIO b2 SRAM |
|
| 4 | K7K1618T2C |
Samsung semiconductor |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM |
|
| 5 | K7K1618U2C |
Samsung semiconductor |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM |
|