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IDTCSPU877A |
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| Part Number | IDTCSPU877A |
| Manufacturer | Integrated Device Technology |
| Description | IDTCSPU877A • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 270MHz • Very low skew: ≤40ps... |
| Features |
DESCRIPTION:
IDTCSPU877A
• 1 to 10 differential clock distribution • Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications • Operating frequency: 125MHz to 270MHz • Very low skew: ≤40ps • Very low jitter: ≤40ps • 1.8V AVDD and 1.8V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 52-Ball VFBGA and 40-pin MLF packages APPLICATIONS: • Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver • Along with SSTU32864/65/66, DDR2 register, p... |
| Document |
 IDTCSPU877A Data Sheet
PDF 179.31KB |
| Distributor | Stock | Price | Buy |
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| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | IDTCSPU877D |
Integrated Device Technology |
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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| 2 | IDTCSPUA877A |
Integrated Device Technology |
1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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| 3 | IDTCSP2510C |
Integrated Device |
3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER |
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| 4 | IDTCSP2510D |
IDT |
3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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| 5 | IDTCSPF2510C |
Integrated Device Technology |
3.3V PHASE-LOCK LOOP CLOCK DRIVER |
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