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M312L2920BG0-CB3 |
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| Part Number | M312L2920BG0-CB3 |
| Manufacturer | Samsung |
| Description | Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Add... |
| Features |
2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. R... |
| Document |
 M312L2920BG0-CB3 Data Sheet
PDF 274.42KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | M312L2920BG0-A2 |
Samsung |
DDR SDRAM Registered Module |
|
| 2 | M312L2920BG0-B0 |
Samsung |
DDR SDRAM Registered Module |
|
| 3 | M312L2920BG0 |
Samsung |
DDR SDRAM Registered Module |
|
| 4 | M312L2920BT |
Samsung |
DDR SDRAM Registered Module |
|
| 5 | M312L2920BTS-A2 |
Samsung |
DDR SDRAM Registered Module |
|