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DM74LS109A |
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| Part Number | DM74LS109A |
| Manufacturer | Fairchild Semiconductor |
| Description | This device contains two independent positive-edge-triggered J-K flip-flops with complementary outputs. The J and K data is accepted by the flip-flop on the rising edge of the clock pulse. The trigger... |
| Features |
ead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X ↑ ↑ ↑ ↑ L J X X X L H L H X K X X X L L H H X Q0 H Q0 Q H L L Toggle Q0 L Q0 Outputs Q L H H
H (Note 1) H (Note 1)
H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↑ = Rising Edge of Pulse Q0 = The output logic level of Q before the indicated input conditions were established. Toggle = Each output changes... |
| Document |
 DM74LS109A Data Sheet
PDF 52.34KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | DM74LS109A |
National Semiconductor |
Dual Positive-Edge-Triggered J-K Flip-Flops |
|
| 2 | DM74LS10 |
Fairchild Semiconductor |
Triple 3-Input NAND Gate |
|
| 3 | DM74LS10 |
National Semiconductor |
Triple 3-Input NAND Gates |
|
| 4 | DM74LS107A |
National Semiconductor |
Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops |
|
| 5 | DM74LS11 |
Fairchild Semiconductor |
Triple 3-Input AND Gate |
|