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CY7C2170KV18 |
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| Part Number | CY7C2170KV18 |
| Manufacturer | Cypress Semiconductor |
| Description | CY7C2168KV18/CY7C2170KV18 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT Feature... |
| Features |
■ 18-Mbit density (1M × 18, 512K × 36) ■ 550-MHz clock for high bandwidth ■ Two-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces (data transferred at 1100 MHz) at 550 MHz ■ Available in 2.5 clock cycle latency ■ Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only ■ Echo clocks (CQ and CQ) simplify data capture in high-speed systems ■ Data valid pin (QVLD) to indicate valid data on the output ■ On-die termination (ODT) feature ❐ Supported for D[x:0], BWS[x:0], and K/K inputs ■ Synchronous internally self-timed writes ■ DDR II+ operate... |
| Document |
 CY7C2170KV18 Data Sheet
PDF 624.09KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | CY7C2163KV18 |
Cypress Semiconductor |
18-Mbit QDR II+ SRAM Four-Word Burst Architecture |
|
| 2 | CY7C2165KV18 |
Cypress Semiconductor |
18-Mbit QDR II+ SRAM Four-Word Burst Architecture |
|
| 3 | CY7C2168KV18 |
Cypress Semiconductor |
18-Mbit DDR II+ SRAM Two-Word Burst Architecture |
|
| 4 | CY7C2245KV18 |
Cypress Semiconductor |
36-Mbit QDR II+ SRAM Four-Word Burst Architecture |
|
| 5 | CY7C225 |
Cypress |
512 x 8 Registered PROM |
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