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IS61DDPB41M18A |
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| Part Number | IS61DDPB41M18A |
| Manufacturer | Integrated Silicon Solution |
| Description | 512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write op... |
| Features |
DESCRIPTION
512Kx36 and 1Mx18 configuration available. On-chip Delay-Locked Loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read and write input ports. 2.5 cycle read latency. Fixed 4-bit burst for read and write operations. Clock stop support. Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ,... |
| Document |
 IS61DDPB41M18A Data Sheet
PDF 560.31KB |
| Distributor | Stock | Price | Buy |
|---|
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | IS61DDPB41M18A1 |
Integrated Silicon Solution |
18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM |
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| 2 | IS61DDPB41M18A2 |
Integrated Silicon Solution |
18Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM |
|
| 3 | IS61DDPB41M36A |
Integrated Silicon Solution |
36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM |
|
| 4 | IS61DDPB41M36A1 |
Integrated Silicon Solution |
36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM |
|
| 5 | IS61DDPB41M36A2 |
Integrated Silicon Solution |
36Mb DDR-IIP(Burst 4) CIO SYNCHRONOUS SRAM |
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