| No. | Partie # | Fabricant | Description | Fiche Technique |
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National Semiconductor Corporation |
Precision Clock Conditioners Low-Noise Clock Jitter Cleaner dual redundant inputs, five differential outputs, and an optional default-clock upon power up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock. Each clock output consists of a program |
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Texas Instruments |
Family Low-Noise Clock Jitter Cleaner 1 •23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Phase Detector Rate of up to 40 MHz – Integrated Low-Noise Crystal Oscillator Circuit – Dual Redundant Input Reference Clock with LOS – PLL2 – Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz – Phase |
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