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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of cl |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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System Logic Semiconductor |
Octal-D Flip-Flop tg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Ai |
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ON Semiconductor |
Octal D Flip-Flop • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirement |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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Texas Instruments |
Octal D-Type Flip-Flop • Common clock and asynchronous controller reset • Positive edge triggering • Buffered inputs • Fanout (over temperature range) – Standard outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range: –55℃ to 125℃ • |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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Toshiba |
Octal D-Type Flip-Flop (1) High speed: fMAX = 67 MHz (typ.) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25 (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC20 ©2016 Toshiba C |
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Fairchild |
Octal D-Type Flip-Flops s Typical propagation delay: 18 ns s Wide operating voltage range s Low input current: 1 PA maximum s Low quiescent current: 80 PA (74 Series) s Output drive: 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC27 |
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nexperia |
Octal D-type flip-flop • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Ideal buffer for MOS microcontroller or memory • Common clock and master reset • Input levels: • For 74AHC273: CMOS level • For 74AHCT |
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nexperia |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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UTC |
OCTAL D-TYPE FLIP-FLOPS * Wide Operating Voltage Range of 2V to 6V * Low Power Consumption, 80-μA Maximum ICC *Typical tPD = 12ns * ±4mA Output Drive at 5V * Low Input Current of 1μA Maximum * Contain Eight Flip-Flops With Single-Rail Outputs * Direct Clear Input * Individu |
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STMicroelectronics |
Rad-hard high speed 2 to 6V CMOS logic • ESCC qualified • 7 V Absolute maximum ratings • 2 V to 6 V operating voltage for CMOS M54HCxxx series • 4.5 V to 5.5 V operating voltage for TTL M54HCTxxx series • Ceramic hermetic packages • -55 °C to +125 °C operating temperature range • Radiatio |
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STMicroelectronics |
Octal D-Type Flip-Flop he other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits a |
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nexperia |
Octal D-type flip-flop • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Ideal buffer for MOS microcontroller or memory • Common clock and master reset • Input levels: • For 74AHC273: CMOS level • For 74AHCT |
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Hitachi Semiconductor |
Octal D-type Flip-Flops (with Clear) • • • • • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25° |
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NIC |
Stacked Film Capacitor Chips • STACKED METALLIZED POLYPHENYLENE SULFIDE (PPS) FILM • STANDARD EIA 0603, 0805, 1206, 1210, 1913 AND 2416 SIZES • WIDE TEMPERATURE RANGE UP TO +125OC (100pF ~ 0.1μF) • HIGH HEAT AND MOISTURE RESISTANT • VERY STABLE TEMPERATURE, FREQUENCY AND VOLTAGE |
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Motorola |
Octal D Flip-Flop 02 20 1 20 1 ORDERING INFORMATION LOGIC DIAGRAM 3 4 7 8 13 14 17 18 19 11 2 5 6 9 12 15 16 MC54HCXXXAJ MC74HCXXXAN MC74HCXXXADW MC74HCXXXADT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 NONINVERTING OUTPUTS Ceramic Plastic SOIC TSSOP D0 D1 D2 DATA INPUTS D3 D4 D5 |
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IK Semiconductor |
Octal D-Type Flip-Flop MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply |
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