AT89C51 डाटा शीट PDF( Datasheet )

Features • Compatible with MCS-51™ Products • 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles • Fully Static Operation: 0 Hz to 24 MHz • Three-level Program M

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K • 2K Byt

Features • 80C51 Core – 12 or 6 Clocks per Instruction (X1 and X2 Modes) – 256 Bytes Scratchpad RAM – Dual Data Pointer – Two 16-bit Timer/Counters: T0 and T1 T83C5121 with 16 Kbytes Mask ROM T85C5121

Features • 80C51 Core : • • • • • • • – 6 Clocks per Instruction – Speed up to 16 MHz 768 Bytes RAM AT83C5122: 32 Kbytes ROM AT83C5123: 30 Kbytes ROM AT85C5122: 32 Kbytes Code RAM and 32 Kby

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters:

Features • 80C52X2 Core (6 Clocks per Instruction) – Maximum Core Frequency 48 MHz in X1 Mode, 24MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T

Features www.DataSheet4U.com • Protocol – USB Used as Physical Layer – Device Firmware Upgrade Class Compliant – USB Clock Auto-Configuration • In-System Programming – Read/Write Flash and EEPROM M